1. Field of the Invention
The present invention relates to a semiconductor apparatus, and more particularly to a structure for protecting a circuit from a surge, such as an electrostatic surge and to a process for manufacturing the semiconductor apparatus.
2. Description of the Related Art
In semiconductor apparatuses, the ESD protection capability needs to be improved to protect an internal circuit from a surge such as an electrostatic surge so that the internal circuit is not destroyed by the static electricity. FIG. 1A shows a first one of the conventional techniques for improving the ESD protection capability of an output buffer to be connected to a pad.
In accordance with the first conventional technique, an output buffer 500 has a drain region 502, a field isolation region 504 provided around at least a portion of the drain region 502, and a channel stopper non-implanted region 506 between the field isolation region 504 and the drain region 502. On the other hand, a channel stopper implanted region (field inversion prevention region) is provided between a source region 508 and the field isolation region 504.
In the first conventional technique, the drain region 502 forms a PN junction with a p-type well of low impurity concentration, not with the channel stopper implanted region of high impurity concentration. Accordingly, junction breakdown voltage can be increased and electrostatic destruction by a surge of static electricity is effectively prevented.
However, the first conventional technique shown in FIG. 1A suffers a problem in which large leak current flows between the drain region 502 and the source region 508 because of the presence of the channel stopper non-implanted region 506.
To solve such a problem of the conventional technique, for example, Japanese Laid-open Patent No. 61-19174 teaches a second one of the conventional technique. According to the second conventional technique, both ends of a gate electrode 510 protrude into a source region 508, as shown in FIG. 1B. When the gate length is relatively long, the second technique lowers the leak current.
However, with the advancement of device size miniaturization, when the gate length (channel length) is shorter than, for example, about 0.35 xcexcm, it has been confirmed that non-negligible amount of leak current flows between the drain region 502 and the source region 508 in the structure shown in FIG. 1B.
The present invention has been made to solve the problems described above, and an object of the present invention is to provide a semiconductor apparatus that secures high ESD protection capability and yet effectively lowers the leak current and to provide a process for manufacturing the semiconductor apparatus.
To achieve the above-described objects, a semiconductor apparatus in accordance with the present invention includes a first region of a first conductivity type, a first impurity region of a second conductivity type formed in the first region having a first edge, a second impurity region of the second conductivity type formed adjacent to the first impurity region and having a second edge arranged opposite to the first edge, the second edge having end portions and an intermediate area, a wiring layer connected to the second impurity region, a field isolation region formed around at least a portion of the second impurity region, and a channel stopper non-implanted region provided between the second impurity region and the field isolation region. The semiconductor device is characterized in the first edge is separated from the second edge at the intermediate area by a distance of L1 and at the end portions by a distance greater than L1, and wherein an end portion of the channel stopper non-implanted region is separated from the first edge at a distance of L2, where L2 is at least L1.
In accordance with the present invention, the ESD protection capability can be improved by the provision of the channel stopper non-implanted region. Also, the end portion (end edge) of the channel stopper non-implanted region is separated from the first edge at a distance of L2, where L2 is at least L1. As a result, the leak current caused by sub-threshold current is reduced. In particular, in accordance with the present invention, leak current is reduced without being substantially affected by even further device miniaturization.
The present invention is also characterized in that cut sections are provided in both end sections of the first edge of the first impurity region and cut sections are provided in both end sections of the second edges. By this configuration, leak current is further securely lowered.
The present invention is further characterized in that the semiconductor apparatus includes a contact for connecting the second impurity region and the wiring layer, wherein the contact is provided on the side of the intermediate area being interior with respect to borders defined between the intermediate area of the second edge and the respective end portions of the second edge where the cut sections are provided. Also, the present invention is characterized in that the semiconductor apparatus includes a metal silicide layer formed on the surface of the second impurity region, wherein the metal silicide layer is provided on the side of the intermediate area being interior with respect to borders defined between the intermediate area and the respective end portions of the second edge where the cut sections are provided. As a result, along edges of the second impurity region extending transverse to the second edge, electrostatic destruction that may be resulted from avalanche breakdown is effectively prevented.
In accordance with the present invention, preferably, the first and second impurity regions are, respectively, a source region and a drain region of an output buffer. Also, the first and second impurity regions may be, respectively, an emitter region and a collector region of a lateral bipolar type protection circuit.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.